Data erasing methods for flash memory are described in Patent Documents 1 and 2. FIG. 6 is a flow chart schematically showing an erase operation in Patent Documents 1 and 2.
With reference to FIG. 6, in a case where data erasure of the flash memory is started, initially, a pulse voltage of a prescribed strength that is independent of a threshold voltage of a memory cell is applied to the memory cell (step S101).
Next, the threshold voltage of the memory cell is determined (step S102). The determination uses an arbitrarily set verify voltage, and employs an erase verify operation (that is, verification of an erased state). In a case where the threshold voltage is not greater than a prescribed voltage (hereinafter termed “erase level”), the memory cell is determined to be in an erased state (Yes in step S102). On the other hand, in a case where the memory cell is determined to be in a non-erased state (No in step S102), a pulse voltage for erasure corresponding to the threshold voltage of the memory cell is applied to the flash memory (step S103).
FIGS. 7A-7C are drawings for describing a conventional data erasing method of a flash memory. FIGS. 7A to 7C schematically show memory cell threshold voltage distribution and data erase pulse voltage.
With reference to FIG. 7A, the threshold voltage distribution d0 is a threshold voltage distribution of a memory cell before starting data erasure. By applying a pulse voltage p1 to the memory cell (step S101), the threshold voltage distribution changes from the threshold voltage distribution d0 to the threshold voltage distribution d1. Next, by sequentially applying pulse voltages p2 to p6 corresponding to threshold voltage (step S103), the threshold voltage distribution sequentially changes to the threshold voltage distributions d2 to d6. At a point in time at which the threshold voltage distribution is d6, when the threshold voltage of the memory cell is determined (step S102), the threshold voltage distribution d6 is not greater than the erase level Vth0 (Yes in step S102), the memory cell is regarded as being in an erased state, and data erasure is completed.
In Patent Documents 1 and 2, by applying the erase pulse voltage corresponding to the threshold voltage of the memory cell, variation in erase time is reduced, erase speed is improved, and excessive voltage stress is not applied to the flash memory.
Patent Document 1:    JP Patent Kokai Publication No. JP2007-323716A
Patent Document 2:    JP Patent Kokai Publication No. JP2008-165960A